Power optimized logic circuit design with a novel synthesis technique

Abstract

The purpose of this paper is to propose a systematic methodology for non-regenerative logic circuit design at the gate level. The tr-aditional logic synthesis methods [5f, [6] become inetfective in ccase of Non-Adjacent Jfnctions. In this paper, we address the redutction problem for this case by evolving a set of minimization lemmas based on the Hamming distance between the terms. Though our main emphasis has been on the satisfiabilitv of the circuiit functionality with minimum number of active gates, the approach presented here takes a viewpoint, in which all critical design metrics are investigated with the primary goal of reducing the dynamic power consunmption of the circuit. The SPICE simulation results obtained on the basis of 3.3V, 0.5,um CMOS technology are very encouraging, as they report minimization in average power consumption by about 36 %for the examples cited, along with a substantial improvement in the Figure oj Merit (FoM) of the circuit, in comparison with that obtainable using conventional approaches.