V. Sessi, H. Mulaosmanovic, R. Hentschel, S. Pregl, T. Mikolajick, W. Weber
{"title":"Junction Tuning by Ferroelectric Switching in Silicon Nanowire Schottky-Barrier Field Effect Transistors","authors":"V. Sessi, H. Mulaosmanovic, R. Hentschel, S. Pregl, T. Mikolajick, W. Weber","doi":"10.1109/NANO.2018.8626257","DOIUrl":null,"url":null,"abstract":"We report on a novel silicon nanowire-based field effect transistor with integrated ferroelectric gate oxide. The concept allows tuning the carrier transport in a non-volatile approach by switching the polarization in the ferroelectric layer close to the source Schottky-junction. We interpret the results in terms of tuning the transmissibility of the Schottky-junction for charge carriers. The experimental results provide a first step towards the integration of memory-in-logic concepts with reconfigurable nanowire transistors.","PeriodicalId":425521,"journal":{"name":"2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANO.2018.8626257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
We report on a novel silicon nanowire-based field effect transistor with integrated ferroelectric gate oxide. The concept allows tuning the carrier transport in a non-volatile approach by switching the polarization in the ferroelectric layer close to the source Schottky-junction. We interpret the results in terms of tuning the transmissibility of the Schottky-junction for charge carriers. The experimental results provide a first step towards the integration of memory-in-logic concepts with reconfigurable nanowire transistors.