Design of an Isolated Gate Driver for Medium Voltage Cascaded H-Bridge (CHB) Based Solid State Transformer (SST)

Surja Sekhar Chakraborty, D. Saravanan, S. Bhawal, K. Hatua
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引用次数: 1

Abstract

The design of an isolated gate driver for a Medium Voltage (MV) Cascaded H-bridge (CHB) converter is proposed in this paper. Isolation with proper electrical insulation and a low common-mode coupling capacitance are considered as the primary design criteria while designing the gate driver. A detailed circuit analysis has been carried out to find the isolation issues in the MV CHB converters, which necessitates a 2ndstage of isolation in the gate driver circuit. Apart from improving the isolation voltage level, the additional isolation stage helps to reduce the coupling capacitance in the common mode path. As the device count for an MV CHB converter is significantly high, the complementary pulses have been generated locally in a CPLD-based delay card, which reduces the count of the optical cables and the associated components. It helps to make the system simple and cost effective. Finally, the design of the proposed gate drivers and associated delay cards are verified in a hardware prototype of 1.65kV/300V, 10kVA Solid State Transformer (SST).
中压级联h桥固态变压器(SST)隔离栅驱动器的设计
提出了一种用于中压级联h桥变换器的隔离栅驱动器的设计。在设计栅极驱动器时,采用适当的电绝缘隔离和低共模耦合电容是主要的设计标准。通过详细的电路分析,找出了中压CHB变换器存在的隔离问题,需要在栅极驱动电路中进行二级隔离。除了提高隔离电压水平外,额外的隔离级还有助于降低共模路径中的耦合电容。由于中压CHB转换器的器件数量非常高,因此互补脉冲在基于cpld的延迟卡中本地产生,从而减少了光缆和相关元件的数量。它有助于使系统简单和经济有效。最后,在1.65kV/300V, 10kVA固态变压器(SST)的硬件样机中验证了所提出的栅极驱动器和相关延迟卡的设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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