LVCMOS based Green Data Flip Flop Design on FPGA

Abstract

An energy and power efficient Data Flip Flop hasbeen designed on FPGA in the following paper in order to meet the energy crises across the globe. Two energy and power efficient techniques have been implemented on device in order to contribute towards Green Communication. One of the techniques is known as Frequency Scaling technique and another one is known as IO Standard Scaling. In both the techniques the total power dissipation by the device has been analyzed and then the least power consumed frequency and IO standard has been find out amongst all the tested frequencies and IOstandards. Out of all the 3 tested frequencies of 1 MHz, 1 GHz and 1 THz, it has been advised to operate the device at a frequency range of MHz as compare to GHz and THz since large amount of power can be saved by using the lower frequency range. Also the device has been tested on 4 different IOstandards of Low Voltage Complementary Metal Oxide Semiconductor (L VCMOS) logic family that are L VCMOS 15, L VCMOS 18, L VCMOS 25 and LVCMOS 33. Out of all 4 tested IOstandards it has been advised to operate the device on L VCMOS 15 since least power is consumed by this IOstandard of L VCMOS logic family as compared to the other IO standard of L VCMOS logic family. In this way by choosing the optimum operating frequency and IO standard, an energy and power efficient device can be designed.