Performance simulator based on hardware resources constraints for ion trap quantum computer

Muhammad Ahsan, Byung-Soo Choi, Jungsang Kim
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引用次数: 5

Abstract

Efforts to build quantum computers using ion-traps have demonstrated all elementary qubit operations necessary for scalable implementation. Modular architectures have been proposed to construct modest size quantum computers with up to 104 - 106 qubits using technologies that are available today (MUSIQC architecture). Concrete scheduling procedure to execute a given quantum algorithm on such a hardware is a significant task, but existing quantum CAD tools generally do not account for the underlying connectivity of the qubits or the limitation on the hardware resources available for the scheduling. We present a scheduler and performance simulator that fully accounts for these resource constraints, capable of estimating the execution time and error performances of executing a quantum circuit on the hardware. We outline the construction of tool components, and describe the process of mapping the qubits to ions and scheduling the physical gates in the MUSIQC architecture. Using this tool, we quantify the trade-off between hardware resource constraints and performance of the computer and show that at an expense of x fold increase in latency, a minimum of 1.6x resource reduction is possible for executing a three-qubit Bernstein-Vazirani algorithm encoded using Steane code.
基于硬件资源约束的离子阱量子计算机性能模拟器
使用离子阱构建量子计算机的努力已经展示了可扩展实现所需的所有基本量子比特操作。模块化架构已被提议使用当今可用的技术(MUSIQC架构)构建具有高达104 - 106个量子位的中等大小的量子计算机。在这样的硬件上执行给定量子算法的具体调度过程是一项重要的任务,但是现有的量子CAD工具通常没有考虑到量子比特的底层连通性或可用于调度的硬件资源的限制。我们提出了一个调度程序和性能模拟器,充分考虑了这些资源限制,能够估计在硬件上执行量子电路的执行时间和错误性能。我们概述了工具组件的构造,并描述了在MUSIQC架构中将量子比特映射到离子和调度物理门的过程。使用此工具,我们量化了硬件资源约束和计算机性能之间的权衡,并表明在延迟增加x倍的代价下,执行使用Steane代码编码的三量子位Bernstein-Vazirani算法至少可以减少1.6倍的资源。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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