Numerical Simulation of FET Transistors Based on Nanowire and Fin Technologies

Abstract

In this work there are presented a results of 3D-numerical simulation of Nanowire FET (NW-FET) and FinFET n-type transistors with “Gate-all-around” and “TRI-GATE” technologies based on “Silicon-on-Insulator” Si-channels. 3D structures are describes and modeled using TCAD Silvaco instruments. There are presented the allowable electrical characteristics in a temperature range of 300–360 K. Numerical simulation has been shown that usage of proposed structures provides permissible values of threshold voltage, sub-threshold swing, drain-induced barrier lowering, drain current and Ion / Ioff ratio. A comparison of working characteristics of simulated structures allows us to conclude that SOI GAA NW-FET had better positions than SOI TG FinFET structures.