A Low-Power Spike Detection and Alignment Algorithm

Abstract

Front-end integrated circuits for signal processing are useful in neuronal recording systems that engage a large number of electrodes. Detecting, alignment, and sorting the spike data at the front-end reduces the data bandwidth and enables wireless communication. Without such data reduction, large data volumes need to be transferred to a host computer and typically heavy cables are required which constrain the patient or test animal. Front-end processing circuits can dissipate only a limited amount of power, due to supply constraints and heat restrictions. Reduced complexity spike detection and alignment algorithm and architecture, based on integral transform, are introduced. They achieve 99% of the precision of a PCA detector, while requiring only 0.05% of the computational complexity