An all digital 650-Mbps demonstration receiver for NASA's high data rate satellite applications

MILCOM 92 Conference Record Pub Date : 1992-10-11 DOI:10.1109/MILCOM.1992.244166

Matthew J. Thompson, W. Jones

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引用次数: 3

Abstract

A demonstration receiver that tracks and demodulates 650-Mb/s QPSK (quadrature phase-shift keying) data has been developed, utilizing a parallel processing VLSI architecture and multirate digital signal processing, to meet upcoming NASA satellite communication requirements. Data rates of 650 Mb/s were achieved with low implementation loss and two-sample/symbol operation using high-speed digital GaAs logic in the front and back end, with the majority of the computationally intensive signal processing implemented in CMOS VLSI. Using a parallel architecture combined with multirate digital signal processing means that receiver speed is no longer limited to the speed of the signal processing hardware elements, but only by the speed of the analog-to-digital converters. In addition to unsurpassed data rate levels, superior bit error rate (BER) performance has been achieved using a joint feedforward and feedback timing estimator and data recovery algorithm. Laboratory performance results for the hardware demonstration receiver are presented as well as a detailed discussion of the hardware implementation and signal processing algorithms.<>

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全数字650-Mbps演示接收机，用于NASA的高数据速率卫星应用

利用并行处理VLSI架构和多速率数字信号处理，开发了一种跟踪和解调650 mb /s QPSK(正交相移键控)数据的演示接收器，以满足即将到来的NASA卫星通信要求。采用高速数字GaAs逻辑在前端和后端实现低实现损耗和双采样/符号运算，数据速率达到650 Mb/s，大部分计算密集型信号处理在CMOS VLSI中实现。采用与多速率数字信号处理相结合的并行架构意味着接收器的速度不再受信号处理硬件元件速度的限制，而只受模数转换器速度的限制。除了无与伦比的数据速率水平外，使用联合前馈和反馈定时估计器和数据恢复算法，还实现了卓越的误码率(BER)性能。给出了硬件演示接收机的实验室性能结果，并详细讨论了硬件实现和信号处理算法

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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MILCOM 92 Conference Record

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