CAD Opportunities with Hyper-Pipelining

M. Iyer
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Abstract

Hyper-pipelining is a design technique that results in significant performance and throughput improvements in latency-insensitive designs. Modern FPGA architectures like Intel's Stratix®10 feature a revolutionary register-rich HyperFlex? core fabric architecture that make it amenable for hyper-pipelining. Design implementation CAD tools can provide insights into performance bottlenecks and how hyper-pipelining can result in improved performance, that can then be implemented using well-known techniques like retiming. Retiming was first introduced as a powerful sequential design optimization technique three decades ago, yet gained limited popularity in the ASIC industry. In recent years, retiming has gained tremendous popularity in the FPGA industry. This talk will discuss why this is the case, and provide insights into some of the interesting opportunities it presents for design implementation, analysis, and verification CAD tools. Impacts of hyper-pipelining on the physical design CAD flow and timing closure will also be discussed.
使用Hyper-Pipelining的CAD机会
超流水线是一种设计技术,可以显著提高延迟不敏感设计的性能和吞吐量。现代FPGA架构,如英特尔的Stratix®10,具有革命性的寄存器丰富的HyperFlex?核心结构架构,使其适合超流水线。设计实现CAD工具可以深入了解性能瓶颈,以及超流水线如何提高性能,然后可以使用重新计时等众所周知的技术来实现。三十年前,重定时首次作为一种强大的顺序设计优化技术被引入,但在ASIC行业的普及程度有限。近年来,重定时在FPGA行业得到了极大的普及。本讲座将讨论为什么会出现这种情况,并提供一些有趣的机会,它为设计实现,分析和验证CAD工具提供了见解。超流水线对物理设计、CAD流程和时序关闭的影响也将被讨论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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