VLSI design of a modulo-extractor

[1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings Pub Date : 1991-05-09 DOI:10.1109/PACRIM.1991.160745

R. Sivakumar, N.J. Dimopulos, K. Li

引用次数: 0

Abstract

A VLSI design of a modulo-extractor based on the principles of residue arithmetic is discussed. A method for computing (X)/sub m/ for specific values of m is analyzed, and the area-time complexity has been implemented in 3 mu m CMOS3DLM technology. Simulation results have yielded a propagation delay of less than 100 ns.<>

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一种模提取器的VLSI设计

讨论了基于残数算法原理的模提取器的VLSI设计。分析了特定m值(X)/sub m/的计算方法，并在3 μ m CMOS3DLM技术上实现了面积-时间复杂度。仿真结果显示，传输延迟小于100纳秒。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

[1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings

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