Task sequencing for optimizing the computation cycle in a timed computation model

Abstract

Recent developments in embedded control systems promote the timed computation model following the principles of logical execution time (LET). Resulting control applications are time deterministic, value deterministic, and their properties may be subject to formal verification against a mathematical model of the control design. However, the timed computation model introduces inefficiencies to computation cycles. As the LET of a real-time control task requires being greater than its worst-case execution time and computed values are always propagated at the end of the LET, actuator updates are unnecessarily delayed. This makes the control cycle less responsive. In this paper, we present an approach that allows the definition of task sequences for a timed computation model implemented by the timing definition language (TDL). Task sequences help minimizing timing delays between sensor readings and actuator updates (e.g., in estimator-based control systems), managing startup and shutdown phases of control systems, and providing mechanisms for error-detection in fault-tolerant systems.