Optimizing network efficiency of dataflow architectures through dynamic packet merging

Abstract

Dataflow processor has shown its unique advantages in executing high performance computing applications with its communication-exposed microarchitecture. In dataflow processors, large amounts of data are directly transferred between instructions through a network-on-chip. The efficiency of data transfer is an imperative performance metric that needs to be optimized in most dataflow processors. Based on the specific features of the dataflow network, we propose a mechanism for dynamically merging the packets in the routers. By testing workloads with varying characteristics, the experiment results demonstrate that the average latency of data transfer is reduced by 11.8%, the performance of dataflow accelerator is improved by 14.0%.