Multiple priority, per flow, dual GCRA rate controller for ATM switches

A. Hagai, B. Patt-Shamir
{"title":"Multiple priority, per flow, dual GCRA rate controller for ATM switches","authors":"A. Hagai, B. Patt-Shamir","doi":"10.1109/HPSR.2001.923626","DOIUrl":null,"url":null,"abstract":"We propose a rate controller for ATM switches. The rate controller supports multiple priorities, and dual leaky bucket (GCRA) traffic descriptors (such as VBR). While regulating each stream independently, our rate controller requires relatively modest computation bandwidth so that it can be implemented without any additional special-purpose hardware. The memory space requirement under reasonable circumstances is close to the most space-efficient schemes. It also enjoys the important advantage of being decoupled from the link scheduler. We analyze the outgoing traffic characteristics of our shaper with combination of strict priority and WFQ link scheduler, and find the optimal shaping parameters so as to maintain conformance at downstream switches. We study the best ways to allocate resources to rate controllers along the path of connection, and demonstrate the effectiveness of aggressive and light shaping in a multiple stage network under various network loads.","PeriodicalId":308964,"journal":{"name":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPSR.2001.923626","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

We propose a rate controller for ATM switches. The rate controller supports multiple priorities, and dual leaky bucket (GCRA) traffic descriptors (such as VBR). While regulating each stream independently, our rate controller requires relatively modest computation bandwidth so that it can be implemented without any additional special-purpose hardware. The memory space requirement under reasonable circumstances is close to the most space-efficient schemes. It also enjoys the important advantage of being decoupled from the link scheduler. We analyze the outgoing traffic characteristics of our shaper with combination of strict priority and WFQ link scheduler, and find the optimal shaping parameters so as to maintain conformance at downstream switches. We study the best ways to allocate resources to rate controllers along the path of connection, and demonstrate the effectiveness of aggressive and light shaping in a multiple stage network under various network loads.
多优先级,每流,双GCRA速率控制器的ATM交换机
提出了一种用于ATM交换机的速率控制器。速率控制器支持多优先级,支持双漏桶(dual leaky bucket, GCRA)流量描述符(如VBR)。在独立调节每个流时,我们的速率控制器需要相对适度的计算带宽,因此它可以在没有任何额外专用硬件的情况下实现。合理情况下的内存空间需求接近于最节省空间的方案。它还享有与链接调度程序解耦的重要优势。结合严格优先级和WFQ链路调度器,分析了整形器的出站流量特性,找到了最优整形参数,以保证下游交换机的一致性。我们研究了沿连接路径将资源分配给速率控制器的最佳方法,并演示了在不同网络负载下多级网络中主动和轻成形的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信