autoVHDL: a domain-specific modeling language for the auto-generation of VHDL core wrappers

Abstract

Reconfigurable embedded hardware is a staple of many applications in defense technology and applied engineering. The integration of various embedded hardware "cores" (i.e., the computing units) is complicated by the unintended complexities inherent in the consistent and correct construction of communication pathways - specified using VHDL. This paper presents a domain-specific modeling approach to reducing this complexity. The results include demonstration of the tool, where generated VHDL code with complex data and processing requirements is simulated.