Vahid Janfaza, B. Forouzandeh, Payman Behnam, M. Najafi
{"title":"Hybrid history-based test overlapping to reduce test application time","authors":"Vahid Janfaza, B. Forouzandeh, Payman Behnam, M. Najafi","doi":"10.1109/EWDTS.2014.7027040","DOIUrl":null,"url":null,"abstract":"In spite of significant efforts in circuit testing, sequential circuit testing has remained a challenging problem. Existing test solutions like scan methods are proposed to facilitate Automatic Test Pattern Generation (ATPG), however, these methods suffer from large area and delay overhead. In this paper, a new hybrid history-based test overlapping method is presented to reduce test time in scan-based sequential circuits while almost no extra hardware overhead is imposed to the circuit. Experimental results show 30% reduction on average test time in comparison with existing works.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2014.7027040","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In spite of significant efforts in circuit testing, sequential circuit testing has remained a challenging problem. Existing test solutions like scan methods are proposed to facilitate Automatic Test Pattern Generation (ATPG), however, these methods suffer from large area and delay overhead. In this paper, a new hybrid history-based test overlapping method is presented to reduce test time in scan-based sequential circuits while almost no extra hardware overhead is imposed to the circuit. Experimental results show 30% reduction on average test time in comparison with existing works.