Hybrid history-based test overlapping to reduce test application time

Vahid Janfaza, B. Forouzandeh, Payman Behnam, M. Najafi
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引用次数: 4

Abstract

In spite of significant efforts in circuit testing, sequential circuit testing has remained a challenging problem. Existing test solutions like scan methods are proposed to facilitate Automatic Test Pattern Generation (ATPG), however, these methods suffer from large area and delay overhead. In this paper, a new hybrid history-based test overlapping method is presented to reduce test time in scan-based sequential circuits while almost no extra hardware overhead is imposed to the circuit. Experimental results show 30% reduction on average test time in comparison with existing works.
混合基于历史的测试重叠,减少测试应用时间
尽管在电路测试方面做出了巨大的努力,但顺序电路测试仍然是一个具有挑战性的问题。现有的测试解决方案,如扫描方法,是为了实现自动测试模式生成(ATPG),但这些方法的缺点是面积大和延迟开销。本文提出了一种新的基于混合历史的测试重叠方法,以减少基于扫描的顺序电路的测试时间,同时几乎不增加电路的额外硬件开销。实验结果表明,与现有工程相比,平均测试时间缩短了30%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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