A Hardware-Efficient HOG-SVM Algorithm and its FPGA Implementation

Abstract

Recently, pedestrian detection has been an important issue in the field of computer vision. To solve the problem of large computation and poor real-time performance in pedestrian detection scene of original histogram of oriented gradients (HOG) algorithm, this paper presents a simplified HOG feature extraction algorithm and an efficient architecture in field programmable gate array (FPGA). This simplified algorithm and Support vector machine (SVM) classifier are successfully implemented on Xilinx Zynq FPGA by using parallelism and pipeline technology. In the feature extraction step, the dimension of HOG feature is reduced by changing the strides of the sliding block, and the complexity of this algorithm and the utilization of hardware resources are reduced. The result shows that this proposed algorithm can achieve 86% true positive rate and 88% precision rate in training stage on INRIA and MIT datasets. The FPGA implementation with pipeline technical and parallel circuit architecture can achieve real-time detect and the simplified algorithm can greatly reduce the utilization of FPGA resources.