Salicide technology for fully-depleted SOI CMOS devices

Abstract

Self-aligned silicide (salicide) is necessary to reduce device resistances associated with an ultra-thin film fully-depleted (UTF/FD) CMOS SOI technology. A salicide process for use with UTF/FD CMOS SOI devices is developed, and subsequent transistor characteristics are shown. Process optimization was achieved through experimental design techniques by minimizing salicide sheet resistance and improving salicide uniformity across the wafer. Replicates at the center points of the experimental designs determined the repeatability of the process and the ability of the models to predict responses. The salicide process developed for SOI is a four-step procedure: (1) Ti deposition (500 AA), (2) monosilicide formation (600-700 degrees C), (3) TiN/Ti removal (1:1 NH/sub 4/OH:H/sub 2/O/sub 2/), and (4) disilicide formation (700-800 degrees C).<>