A simulation study of DS3 waiting time jitter accumulation in SONET

Abstract

Statistical results are presented for DS3 signals crossing cascaded chains of SONET island networks, based on a computer-aided waiting time jitter accumulation model. The parameters of a phase-spreading desynchronizer circuit, necessary to control the additional jitter caused by pointer adjustments, are characterized in terms of jitter accumulation performance. Simulation results and analysis for both nondegraded and degraded network synchronization modes are given, including the effect of pointer adjustments. With special consideration given to certain phase spreading desynchronizer design parameters, the jitter accumulation characteristics for DS3 signals in SONET are well behaved for the example SONET study network.<>