Pseudo-Resistor based Low-Power Differential Voltage Comparator

Abstract

This paper mainly proposes a low-power Differential Voltage Comparator (DVC) design using digital gates to introduce automation in analog circuit design. Therefore, a differential pseudo-resistive based comparator is designed to achieve low power and compatibility in layout process. In the proposed pseudo-resistive comparator, the power consumption is 374 $\mu$W at supply voltage of 1. SV, input frequency is 10Mhz. The power saving is 31.75% as compared with existing digital based comparator. The comparator is designed using CADENCE. The comparator is created using digital cells such as inverters, exclusive-or and tri-state inverters are constructed using CMOS transistors.