Design of Baseband Analog with Filter Tuning for 5.8GHz DSRC Transceiver in ETCS

Abstract

This paper introduces a design of baseband analog with high performance IRR (Image Rejection Ratio) to using wide-bandwidth for DSRC (Dedicated Short Range Communication) transceiver. In addition, an automatic filter tuning system has applied to in this circuit for higher PVT tolerance and accuracy of bandwidth. To reduce adjacent interferers and image signal in baseband circuit, Complex Band Pass Filter (BPF) is used in this system. Baseband analog has high performance of IRR 66.5 dB at 3-dB bandwidth and the Intermediate Frequency (IF) are 10MHz. This circuit is designed in 130nm CMOS process. Power consumption is 7.46mW under 1.2V power supply.