Fault Simulation on Message Passing

Proceedings of the Fifth Distributed Memory Computing Conference, 1990. Pub Date : 1990-04-08 DOI:10.1109/DMCC.1990.555359

Izendert Huisman, Indira Nair, I. B. M. T. J. Watson, Raja Daoud

引用次数: 1

Abstract

A new parallelization technique for Fault Simulation is described that is suited for message passing based parallel processors. The problem is parallelized by first casting it in Dataflow form and then constructing a Dataflow emulator for message passing systems. A fault simulator for combinational logic has been implemented on a Transputer based parallel processor, the IBM VICTOR multiprocessor. Overall performance has been measured for several logic designs.

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消息传递的故障模拟

提出了一种适用于基于消息传递的并行处理器的故障仿真并行化技术。首先将该问题转换为数据流形式，然后为消息传递系统构建数据流仿真器，从而实现该问题的并行化。在基于Transputer的并行处理器IBM VICTOR多处理器上实现了一个用于组合逻辑的故障模拟器。已经测量了几种逻辑设计的总体性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the Fifth Distributed Memory Computing Conference, 1990.

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