Fully parallel FPGA Implementation of an Artificial Neural Network Tuned by Genetic Algorithm

Abstract

An artificial neural network (ANN)-based method for radio-frequency analog circuit synthesis is implemented on a field-programmable gate array (FPGA). The ANN has four hidden layers, with fifteen neurons per hidden layer, and its hyper parameters are tuned by an auxiliary genetic algorithm (GA) that uses deterministic tournament for generation renewal with minimal hardware. The presented work actualizes the inherently parallel nature of ANN processes, doing away with optimizing vector manipulations by conventional serial hardware. Instead, the effort is put on minimizing the resources used by each neuron and maximizing their collective processing power. Moreover, the GA algorithm for hyper parameter tuning is implemented as a parallel process as well. The proposed architecture is validated on a concrete problem, showing its ability to learn the solution to a problem and generalize it to new instances.