Low power and area efficient implementation of N-phase non overlapping clock generator using GDI technique

Abstract

This paper proposes a low power implementation of a non-overlapping clock (NOC) generator based on area efficient realization of Gate-Diffusion-Input (GDI) D flip-flops. The design is programmable for the number of required phases of the NOC and the amount of non-overlap period, legitimate over the wide range of frequency. The derived clocking scheme can be used for various dynamic or multi-phase clocked logic gates to decrease complexity and increase speed. The benefits derived proportionate multi-folds when utilized for low frequency bio-medical applications. Simulation results stand unanimous suggesting the design to be area and power efficient while maintaining a low complexity of logic design. Process and temperature invariance adds its acceptability over a wide range of applications. Various alternate realizations of NOC generator are proposed based on design requirements.