Multi-level concurrent simulation

Abstract

As the size and complexity of logic designs become increasingly large, computing resources to verify the correctness of systems on a chip and develop quality test patterns for manufacturing are becoming strained. Using behavioral models in simulation captures the functional characteristics of a design block without necessarily relying on a specific implementation. Models can be interchanged or replaced by abstracted models as more detailed models become available or as more high level system testing is required. This will allow larger systems to be simulated as a cohesive unit. In addition, by utilizing function lists to dynamically create faulty behaviors, we will demonstrate its versatility for fault simulating multilevel models. In this paper, we investigate behavioral fault simulation and discuss the architecture that provides greater accuracy for a more thorough system level simulation.