Future waferlevel CSP packaging

Abstract

The requirements for wafer-level CSP technology concerning reliability and cost are discussed. A simple cost calculation based on cost per I/O for single chip packaging demonstrates the advantage of wafer-level CSP-type packaging and gives a cost limit for wafer-level packaging technologies. The geometrical limitations are noted. The reliability requirements for successful implementation are described. A wafer-level packaging concept called Diepack is used to study the requirements for wafer-level packaging. It is shown that wafer-level CSP-type packaging can be achieved with "simple" technologies for small dice.