A new design partitioning approach for low power high-level synthesis

Abstract

The optimization of power consumption at a very high design level is a critical step towards a power-efficient digital system design. The increasing usage of battery-powered and often wireless portable systems is driving the demand for IC and SoC devices consuming the smallest possible amount of power. The aim of the method presented in this paper is to integrate low power methods within the scheduling process of the high-level synthesis by defining partitions. Starting from a controlled-data-flow-graph (CDFG) the proposed method uses standard scheduling techniques and path analysis on the graph to identify regions that can be combined to partitions. Each partition has a controlled activation or deactivation mechanism. That mean, the partition can be switched off when it is not used. As an example design, a part of the MPEG-2 algorithm is used.