Relocatable Partial Bitstreams For Virtual Overlay Architectures atop Field-Programmable Gate Arrays

Abstract

Intermediate virtual architecture overlays atop physical FPGA chips provide convenient abstraction level, which can increase productivity in FPGA-targeted application development. Individual reconfigurable modules of the overlay can be reprogrammed independently using partial reconfiguration. Homogeneous reconfigurable modules can be programmed using common configuration data, on condition that appropriate implementation constraints and proper floorplanning of the virtual architecture are provided. This paper presents methodology that can be used to generate relocatable bitstreams for Xilinx 7 series FPGA devices. The methodology is based on using constraints to force Xilinx Vivado Design Suite tools to implement multiple reconfigurable partition in the same way. Partial Reconfiguration Flow is used to implement multiple variants of individually reconfigurable partitions and Isolation Design Flow is used for feed-through prevention.