Yuta Akiya, Kyle Le, Megan Luong, Justin C. Wilson, A. S. Eddin, Valerio Formicola, Mohamed El-Hadedy
{"title":"SHA-3-LPHP: Hardware Acceleration of SHA-3 for Low-Power High-Performance Systems","authors":"Yuta Akiya, Kyle Le, Megan Luong, Justin C. Wilson, A. S. Eddin, Valerio Formicola, Mohamed El-Hadedy","doi":"10.1109/ISSREW53611.2021.00107","DOIUrl":null,"url":null,"abstract":"In the last decade, the world transitioned from using Secure Hash Algorithm 1 (SHA-1) to Secure Hash Algorithm 2 (SHA-2) due to the flaws in SHA-1. However, SHA-2 still uses a similar internal structure with the same mathematical flaws as its predecessor. Safety in SHA-2 is attributed to the increased length of its output compared to SHA-1. Since then, a new hashing algorithm, SHA-3 has been introduced, which does not share the same flaws as its other family members. However, the transition to SHA-3 has not been complete due to lack of software and hardware support for SHA-3 as well as performance issues. The performance limitation, however, is only present in software implementations. In this paper, we propose a new implementation of SHA-3 based on FPGA hardware (SHA-3-LPHP), to be integrated in the architecture of low-power devices. SHA-3-LPHP achieves three orders magnitude improvement in execution time as compared to full software implementations, furthermore, requiring less energy, hence making it an excellent candidate for low-power and high-performance systems.","PeriodicalId":385392,"journal":{"name":"2021 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSREW53611.2021.00107","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In the last decade, the world transitioned from using Secure Hash Algorithm 1 (SHA-1) to Secure Hash Algorithm 2 (SHA-2) due to the flaws in SHA-1. However, SHA-2 still uses a similar internal structure with the same mathematical flaws as its predecessor. Safety in SHA-2 is attributed to the increased length of its output compared to SHA-1. Since then, a new hashing algorithm, SHA-3 has been introduced, which does not share the same flaws as its other family members. However, the transition to SHA-3 has not been complete due to lack of software and hardware support for SHA-3 as well as performance issues. The performance limitation, however, is only present in software implementations. In this paper, we propose a new implementation of SHA-3 based on FPGA hardware (SHA-3-LPHP), to be integrated in the architecture of low-power devices. SHA-3-LPHP achieves three orders magnitude improvement in execution time as compared to full software implementations, furthermore, requiring less energy, hence making it an excellent candidate for low-power and high-performance systems.