{"title":"Wafer fabrication ion implant charging-impact on gate oxide breakdown","authors":"T. Yeoh, Shze-Jer Hu","doi":"10.1109/SMELEC.1998.781153","DOIUrl":null,"url":null,"abstract":"Process induced charging is not new in the wafer fabrication process. However, it is difficult to identify as test structures used cannot detect this problem effectively, as these structures are not connected to large metal or polysilicon networks for charge collection, or if these structures are covered by thick photoresist. Ion implantation is a major process where charging poses a problem to the extent of transistor gate oxide breakdown or degradation. This is presented along with the respective charging models for these phenomena. This breakdown is strongly influenced by device design layout, implanter energy and diffusion breakdown strengths.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.1998.781153","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Process induced charging is not new in the wafer fabrication process. However, it is difficult to identify as test structures used cannot detect this problem effectively, as these structures are not connected to large metal or polysilicon networks for charge collection, or if these structures are covered by thick photoresist. Ion implantation is a major process where charging poses a problem to the extent of transistor gate oxide breakdown or degradation. This is presented along with the respective charging models for these phenomena. This breakdown is strongly influenced by device design layout, implanter energy and diffusion breakdown strengths.