Accumulative parallel counters

Abstract

An accumulative parallel counter represents a true generalization of a sequential counter in that it incorporates the memory feature of an ordinary counter; i.e., it adds the sum of its n binary inputs to a stored value. We examine the design of accumulative parallel counters and show that direct synthesis of such a counter, as opposed to building it from a combinational parallel counter and a fast adder, leads to significant reduction in complexity and delay. While the mere fact that savings can be achieved comes as no surprise to seasoned arithmetic designers, its extent and consequences in designing large-scale (systolic) associative processors, modular multi-operand adders, serial-parallel multipliers, and digital neural networks merits detailed examination. Both simple accumulative parallel counters and their modular versions, that keep the accumulated count module an arbitrary constant p, are dealt with.