MOS Current Mode Logic (MCML) based techniques for D-Flip Flop in 180 nm Technology using LTspice

Abstract

This paper presents various high-speed and low-power MOS Current Mode Logic (MCML) techniques for designing D-latch and D Flip-flop. With the recent technological advancements MCML technique is a novel and better approach on many accounts than the well-known CMOS technique. Various MCML topologies like Conventional, Tripletail, Folded, Rail to Rail, etc. are simulated, analyzed, and compared with the help of LTspice software on 180nm technology. LTspice software offers a user-friendly interface that operates on a simple computational platform. Analysis and comparisons are drawn based on factors like power dissipation and RMS noise. The study is useful for the design of Dynamic current mode D Flip-Flop having very low power dissipation, noise margin, and more minor delays at high-frequency simulations.