The concept of superprocesses for high-level synthesis and their VHDL modelling

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410680

P. Keresztes, I. Agotai

引用次数: 3

Abstract

The authors describe a process with a concurrent control flow as a superprocess. A combined VHDL and data/control flow graph description is proposed so as to create abstract level behavioral specifications containing a concurrent control flow. The functions of the simulation compiler are exposed.<>

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高级综合的超过程概念及其VHDL建模

作者将具有并发控制流的进程描述为超进程。提出了一种结合VHDL和数据/控制流图描述的方法，以创建包含并发控制流的抽象级行为规范。揭示了仿真编译器的功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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