A Hardware-Based Approach to Determine the Frequently Accessed DRAM Pages for Multi-Core Systems

Abstract

It is likely that processor performance improvements will continue to outpace the improvements in memory latency. As processor architectures have been evolved, memory latency has become increasingly an obstacle in achieving optimal application performance. In this paper, a new Hardware-based approach is introduced to determine at run-time the DRAM pages that are frequently accessed (hot DRAM pages). This approach would be an effective and low-cost solution designed primarily to be used with other DRAM memory latency reduction mechanisms. Our experimental results reveal that the prediction accuracy of the hot DRAM pages at run-time obtained by our proposed approach is 88.1 % using a 256-entry history table.