Compact testing with intermediate signature analysis

Abstract

Among a number of techniques for efficiently testing VLSI circuits, the BIST using compression technique is recognized as reliable and cost effective. While compact testing using signature analysis allows an efficient test, some faulty responses cannot be detected due to aliasing. This paper shows how the aliasing probability can be significantly reduced by a factor of 2/sup (k+1)/ when k intermediate signatures are checked. The proposed scheme can also quickly detect the fault using fewer hardware resources.<>