{"title":"FreshCache: Statically and dynamically exploiting dataless ways","authors":"Arkaprava Basu, Derek Hower, M. Hill, M. Swift","doi":"10.1109/ICCD.2013.6657055","DOIUrl":null,"url":null,"abstract":"Last level caches (LLCs) account for a substantial fraction of the area and power budget in many modern processors. Two recent trends - dwindling die yield that falls off sharply with larger chips and increasing static power - make a strong case for a fresh look at LLC design. Inclusive caches are particularly interesting because many commercially successful processors use inclusion to ease coherence at a cost of some data being stale or redundant. Prior works have demonstrated that LLC designs could be improved through static (at design time) or dynamic (at runtime) use of “dataless ways”. The static dataless ways removes the data-but not tags-from some cache ways to save energy and area without complicating inclusive-LLC coherence. A dynamic version (dynamic dataless ways) could dynamically turn off data, but not tags, effectively adapting the classic selective cache ways idea to save energy in LLC but not area. We find that (a) all our benchmarks benefit from dataless ways, but (b) the best number of dataless ways varies by workload. Thus, a pure static dataless design leaves energy-saving opportunity on the table, while a pure dynamic dataless design misses area-saving opportunity. To surpass both pure static and dynamic approaches, we develop the FreshCache LLC design that both statically and dynamically exploits dataless ways, including a predictor to adapt the number of dynamic dataless ways as well as detailed cache management policies. Results show that FreshCache saves more energy than static dataless ways alone (e.g., 72% vs. 9% of LLC) and more area by dynamic dataless ways only (e.g., 8% vs. 0% of LLC).","PeriodicalId":398811,"journal":{"name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 31st International Conference on Computer Design (ICCD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2013.6657055","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Last level caches (LLCs) account for a substantial fraction of the area and power budget in many modern processors. Two recent trends - dwindling die yield that falls off sharply with larger chips and increasing static power - make a strong case for a fresh look at LLC design. Inclusive caches are particularly interesting because many commercially successful processors use inclusion to ease coherence at a cost of some data being stale or redundant. Prior works have demonstrated that LLC designs could be improved through static (at design time) or dynamic (at runtime) use of “dataless ways”. The static dataless ways removes the data-but not tags-from some cache ways to save energy and area without complicating inclusive-LLC coherence. A dynamic version (dynamic dataless ways) could dynamically turn off data, but not tags, effectively adapting the classic selective cache ways idea to save energy in LLC but not area. We find that (a) all our benchmarks benefit from dataless ways, but (b) the best number of dataless ways varies by workload. Thus, a pure static dataless design leaves energy-saving opportunity on the table, while a pure dynamic dataless design misses area-saving opportunity. To surpass both pure static and dynamic approaches, we develop the FreshCache LLC design that both statically and dynamically exploits dataless ways, including a predictor to adapt the number of dynamic dataless ways as well as detailed cache management policies. Results show that FreshCache saves more energy than static dataless ways alone (e.g., 72% vs. 9% of LLC) and more area by dynamic dataless ways only (e.g., 8% vs. 0% of LLC).
在许多现代处理器中,最后一级缓存(llc)占面积和功率预算的很大一部分。最近的两个趋势——随着芯片尺寸的增大,芯片产量急剧下降,以及静态功率的增加——为重新审视有限责任设计提供了强有力的理由。包容性缓存特别有趣,因为许多商业上成功的处理器使用包容性来减轻一致性,代价是一些数据过时或冗余。先前的工作已经证明,LLC设计可以通过静态(在设计时)或动态(在运行时)使用“无数据方式”来改进。静态无数据方式从某些缓存方式中删除数据(而不是标签),以节省能源和面积,而不会使包含llc一致性复杂化。动态版本(动态无数据方式)可以动态地关闭数据,但不关闭标签,有效地采用了经典的选择性缓存方式的思想,以节省LLC而不是面积的能量。我们发现(a)我们所有的基准测试都受益于无数据方式,但是(b)无数据方式的最佳数量因工作负载而异。因此,纯静态的无数据设计留下了节能的机会,而纯动态的无数据设计失去了节省面积的机会。为了超越纯静态和动态方法,我们开发了FreshCache LLC设计,该设计静态和动态地利用无数据方式,包括一个预测器来适应动态无数据方式的数量以及详细的缓存管理策略。结果表明,FreshCache比单独的静态无数据方式节省更多的能源(例如,72% vs. 9%的LLC),并且仅通过动态无数据方式节省更多的面积(例如,8% vs. 0%的LLC)。