A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes

M. Rovini, Giuseppe Gentile, F. Rossi, L. Fanucci
{"title":"A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes","authors":"M. Rovini, Giuseppe Gentile, F. Rossi, L. Fanucci","doi":"10.1109/GLOCOM.2007.620","DOIUrl":null,"url":null,"abstract":"This paper describes a scalable IP of a decoder for LDPC codes compliant to IEEE 802.1 In and running the well- known layered decoding algorithm. The decoder architecture is arranged in clusters of serial processing units, which are configurable to process all the codes in the standard and, at the same time, to support multiple frame decoding. An optimization methodology of the iteration latency is also described, which relates to the order of the messages updated by the processors, as well as to the sequence of layers the decoder goes through. The logic synthesis on 65 nm CMOS technology with low- power standard-cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 180 to 410 Mbps, and the power consumption being below 235 mW.","PeriodicalId":370937,"journal":{"name":"IEEE GLOBECOM 2007 - IEEE Global Telecommunications Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE GLOBECOM 2007 - IEEE Global Telecommunications Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLOCOM.2007.620","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 36

Abstract

This paper describes a scalable IP of a decoder for LDPC codes compliant to IEEE 802.1 In and running the well- known layered decoding algorithm. The decoder architecture is arranged in clusters of serial processing units, which are configurable to process all the codes in the standard and, at the same time, to support multiple frame decoding. An optimization methodology of the iteration latency is also described, which relates to the order of the messages updated by the processors, as well as to the sequence of layers the decoder goes through. The logic synthesis on 65 nm CMOS technology with low- power standard-cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 180 to 410 Mbps, and the power consumption being below 235 mW.
IEEE 802.11n LDPC码的可扩展解码器架构
本文介绍了一种可扩展IP的LDPC码译码器,该译码器符合ieee802.1 In标准,并运行著名的分层译码算法。解码器结构以串行处理单元集群的形式排列,可配置处理标准中的所有编码,同时支持多帧解码。还描述了迭代延迟的优化方法,该方法与处理器更新消息的顺序以及解码器经过的层的顺序有关。基于65 nm CMOS技术和低功耗标准单元库的逻辑综合表明,该设计适用于便携式器件,吞吐量在180 ~ 410 Mbps之间,功耗在235 mW以下。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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