EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper)

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI:10.1109/ASP-DAC52403.2022.9712519

Jiaxi Zhang, Qiuyan Gao, Yijiang Guo, Bizhao Shi, Guojie Luo

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引用次数: 1

Abstract

Multiplier-accumulator (MAC) is a crucial arithmetic element widely used in digital integrated circuits. Customized MACs are necessary for different scenarios but need great effort due to the huge architecture design space. In this paper, we develop EasyMAC, a flexible Chisel-based MAC generator with a canonical architectural representation. We design a compact and canonical sequence representation to express the architecture of MACs. And the MAC generator takes the compact representation as input to gain the Verilog codes. We also give a case study on developing a heuristic design space exploration (DSE) method based on this representation. The experimental result shows the effectiveness of the representation in DSE. Using the percent relative range of the power-delay-area product as a metric to measure the optimization opportunities that this representation exposes, the relative range is 17.4% and 23.1% for 16×16 and 25×18 MACs, respectively. At last, we discuss some promising directions of EasyMAC.

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EasyMAC:使用规范的体系结构表示设计可探索的乘法器-累加器生成器(特邀论文)

乘法器-累加器(MAC)是数字集成电路中广泛应用的关键算法元件。不同的场景需要定制mac，但由于架构设计空间巨大，需要付出很大的努力。在本文中，我们开发了EasyMAC，一个灵活的基于chisel的MAC生成器，具有规范的体系结构表示。我们设计了一个紧凑和规范的序列表示来表达mac的体系结构。MAC生成器将压缩表示作为输入来获得Verilog码。我们还给出了一个基于这种表示的启发式设计空间探索(DSE)方法的案例研究。实验结果表明了该方法在DSE中的有效性。使用功率延迟面积乘积的相对范围百分比作为度量此表示所暴露的优化机会的指标，16×16和25×18 mac的相对范围分别为17.4%和23.1%。最后讨论了EasyMAC的发展方向。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)

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