Power and delay comparison of binary and quaternary arithmetic circuits

Abstract

Interconnections play a crucial role in todays deep sub-micron designs because they dominate the delay, power and area. This is especially critical for modern million-gates FPGAs, where as much as 90% of chip area is devoted to interconnections. Multiple-valued logic allows for the reduction of the required number of signals in the circuit, hence can serve as a means to effectively curtail the impact of interconnections. We present in this paper a comparison of binary and quaternary implementations of arithmetic modules based on lookup table structures using a voltage-mode circuits. Our assessment demonstrates that significant a power reduction is possible through the use of quaternary structures, with very low delay penalties.