An efficient method to evaluate 4 million micro-bump interconnection resistances for 3D stacked 16-mpixel image sensor

Abstract

We developed an efficient method for evaluating the 4 million micro-bump interconnection resistances of the 3D stacked 16-Mpixel CMOS image sensor by including vertical scanning and readout circuits and extra circuits in both of two substrates for a resistance testing mode, which enables us not only to find failed bumps but also to evaluate the resistances by scanning all micro bumps. We measured the resistances of the interconnections ranging from 50 to 500 kΩ with a resolution of 50kΩ.