FPGA implementation of hardware voter

Abstract

In this paper hardware structure of voting unit for mid-value selection is presented. In the process of the hardware design it is very important to regulate the operation of control logic, especially when it is separated into several independent blocks. This paper shows the manner of hardware mid-value select architecture (HMVSA) control logic coupling. Realization of HMVSA assumes ASIC chip implementation, and further integration within fault tolerant data acquisition systems (FTDAS). The final step of this approach assumes the process of HMVSA synthesis and implementation of the FPGA chip.