Automatic layout procedures for serial routing devices

Abstract

Conventional automatic layout systems for MOS or bipolar devices systems cannot deal with certain features, e.g. signal serialization, in serial routing devices such as Josephson devices. The authors define layout requirements and present new automatic layout procedures for such devices. These procedures are based on it subnet partitioning. They can be applied to the hierarchical design of both masterslice and custom logic LSIs. Experiments using four-bit-full-adder circuits confirm their feasibility.<>