A 952MS/s Max-Log MAP Decoder Chip using Radix-4 × 4 ACS Architecture

Abstract

In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13 mum CMOS chip implementation, the decoder occupies 1.96 mm2 area containing 220 K gates. The estimated timing under the 1.08 V supply and the worst case corner shows that the test chip can achieve the maximum 952 MS/s throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.