ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects

Eric S. Chung, Michael Papamichael
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引用次数: 5

Abstract

Today's FPGAs lack dedicated on-chip memory interconnects, requiring users to (1) rely on inefficient, general-purpose solutions, or (2) tediously create an application-specific memory interconnect for each target platform. The CoRAM architecture, which offers a general-purpose abstraction for FPGA memory management, encodes high-level application information that can be exploited to generate customized soft memory interconnects. This paper describes the ShrinkWrap Compiler, which analyzes a CoRAM application for its connectivity and bandwidth requirements, enabling synthesis of highly-tuned area-efficient soft memory interconnects.
ShrinkWrap:软内存互连的编译器启用优化和定制
今天的fpga缺乏专用的片上存储器互连,要求用户(1)依赖低效的通用解决方案,或(2)为每个目标平台繁琐地创建特定于应用程序的存储器互连。CoRAM架构为FPGA内存管理提供了一种通用的抽象,对高级应用程序信息进行编码,这些信息可用于生成定制的软内存互连。本文描述了ShrinkWrap编译器,它分析了CoRAM应用程序的连接性和带宽需求,从而实现了高度调优的区域高效软内存互连的合成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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