Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters

Abstract

This paper deals with the problem of clock skew errors in time-interleaved analog-to-digital converters. Deterministic sample-time errors between time-interleaved channels generate nonlinear distortion and degrade SFDR. We propose a fully digital calibration method that uses, on the one hand, adaptive FIR filters to reconstruct a correctly sampled signal and, on the other hand, a new blind clock skew detection algorithm that guides the adaptive filters. This calibration method applies to any number of parallel channels in a time-interleaved architecture. Here, we show theoretical analysis and simulation results for 4 channels case. It is concluded that the calibration technique can greatly attenuate the spurs and improve the SNDR.