A trace-driven analytical model with less profiling overhead for DRAM access latencies

Abstract

Due to the painful time consuming of cycle-accurate simulations, analytical modeling of DRAM systems has been becoming an effective alternative to give guidance for architecture optimizations. Some analytical models forecast the DRAM performance by obtaining the proportions of different DRAM command appearances from memory trace profiling. However, existing works require too many cases composed by different DRAM commands which need lots of profiling and consume much of time. On the flip side, other methods assume that the arrival process of memory requests to the DRAM satisfies the Poisson distribution and estimate the DRAM performance based on the queueing theory. The assumption, however, will be shown not accurate by our experiments in this paper. Not surprisingly, the performance forecasting based on these models is not accurate, not to mention the cases that some researchers assume the DDR access latency as an empirical constant value. Hence, in this paper, we propose a trace-driven analytical model to quickly and precisely estimate the DDR access latency. Compared to prior studies, our model requires much less time overhead without sacrificing the forecasting precision. 17 benchmarks are adopted for the accuracy evaluation of our model. Compared with the simulation results using Gem5 and DRAMSim2, the average accuracy of our model is higher than 93.31%, while the forecasting process can be sped up by x22 times contrast to cycle-accurate simulations.