5 GHz /spl Sigma//spl Delta/ analog-to-digital converter with polarity alternating feedback comparator

Abstract

We designed and fabricated a 5 GHz oversampling, 100 MHz bandwidth continuous time second order /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using 0.4-/spl mu/m InGaP/-InGaAs enhancement and depletion mode high electron mobility transistor (E/D HEMT) technology. We propose the polarity alternating feedback (PAF) technique for enhancing the sampling frequency and have applied it in the design of an ADC circuit. The fabricated ADC shows a signal-to-noise ratio (SNR) of 43 dB (7.3 bits) under a differential clock of 4.9 GHz with a power dissipation of 400 mW.