A Heuristic Tree Algorithm with a Revocation Based GA for Test Pattern Generation of VLSI Circuits

Abstract

Increasing complexity of VLSI circuits has led to a progressive need for an efficient test generation method that ensures a fault-free performance of the circuit-under-test. The revocation based genetic algorithm which we suggested before had resulted in higher fault coverage and shorter computational time in comparison with previous test pattern generation systems. In this paper we suggest a new heuristic tree algorithm for test pattern generation which works in combination with the revocation based genetic method. Simulations done on ISCAS'85 benchmarks confirm the efficiency of the algorithm and its significant promotion in comparison with the GAs and other previous test pattern generation methods.