A design-for-testability technique for detecting delay faults in logic circuits

Abstract

This paper provides a simulation-based study of the delay fault testing in logic circuits. It is shown that delay testing is necessary in order to achieve a high defect coverage. By detecting delayed time response in a transistor circuit, three types of faults are detected: (1) faults which cause delayed transitions at the output node due to some open defects, (2) faults which cause an intermediate voltage level at the output node, and (3) most stuck-at faults which halt the circuit at '1' or '0'. An on-line checker is presented which enables the concurrent detection of delay faults. Since one checker is used for each output signal, the area overhead is minimal. This technique does not degrade the speed of the circuit under test (CUT). We show that the test circuit is independent of the size of the CUT. Simulation results show that this technique can be adjusted to fit to any design style.