Prashanth R A, Adithya Rangan C K, A. Sreenivasan, Siddappa P Odeyar, V. Kulkarni, Aravinda K Holla
{"title":"Data Rate Engine for USB 2.0 Based Bulk IN and OUT Transactions","authors":"Prashanth R A, Adithya Rangan C K, A. Sreenivasan, Siddappa P Odeyar, V. Kulkarni, Aravinda K Holla","doi":"10.1109/ICAIT47043.2019.8987372","DOIUrl":null,"url":null,"abstract":"USB 2.0 is a serial communication protocol standard which connects peripherals like keyboards, mouse, cameras, audio devices like speakers and microphones, and other electronic devices like mass storage devices. Theoretically, USB 2.0 has defined a target of high speed data rate of 480Mbps, full speed data rate of 12Mbps and low speed data rate of 1.5Mbps. Hence, there arises a need to satisfy functional and speed requirements in the design and implementation of the USB 2.0 IP. This leads towards introducing a system that analyses the IP performance matching the protocol specifications. This paper depicts application of a data rate engine for bulk transfers of USB 2.0 protocol based transfers between host and device. The data rate engine consists of traffic analyzer, data rate calculator and performance tracker. The traffic analyzer recognizes different packets of the USB 2.0 transactions while keeping track of the data flow and related information. The data rate calculator acts as a plug-in to calculate the speed of transactions, additionally assisted by display unit to keep a record of obtained results. The performance tracker helps to understand the variation in data rate with respect to different factors affecting the IP performance. The implementation of data rate engine is in SystemVerilog in Linux platform and the corresponding behavior is identified through testcase simulations.","PeriodicalId":221994,"journal":{"name":"2019 1st International Conference on Advances in Information Technology (ICAIT)","volume":"248 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 1st International Conference on Advances in Information Technology (ICAIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAIT47043.2019.8987372","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
USB 2.0 is a serial communication protocol standard which connects peripherals like keyboards, mouse, cameras, audio devices like speakers and microphones, and other electronic devices like mass storage devices. Theoretically, USB 2.0 has defined a target of high speed data rate of 480Mbps, full speed data rate of 12Mbps and low speed data rate of 1.5Mbps. Hence, there arises a need to satisfy functional and speed requirements in the design and implementation of the USB 2.0 IP. This leads towards introducing a system that analyses the IP performance matching the protocol specifications. This paper depicts application of a data rate engine for bulk transfers of USB 2.0 protocol based transfers between host and device. The data rate engine consists of traffic analyzer, data rate calculator and performance tracker. The traffic analyzer recognizes different packets of the USB 2.0 transactions while keeping track of the data flow and related information. The data rate calculator acts as a plug-in to calculate the speed of transactions, additionally assisted by display unit to keep a record of obtained results. The performance tracker helps to understand the variation in data rate with respect to different factors affecting the IP performance. The implementation of data rate engine is in SystemVerilog in Linux platform and the corresponding behavior is identified through testcase simulations.