Functional Verification Measures to Challenge State Retention Strategy for Inaccessible Power-Gating of Low Power IPs

Abstract

The Power Management and Control Unit (PMCU) plays a crucial role in optimizing power for both simple and complex SoCs which house for at least a few low power IPs. It requires extensive validation across the window of power transition from ungated to gated domain and vice-versa. The technologies through which the domain-based power requirement of individual IPs in an SoC is met, are mostly isolation and retention. Since physical flops are involved in these implementations, consideration is often subjected to area and gate-count budget of a IP and it is expected to be as minimum as possible for a low-power-low-speed serial-peripheral like a sensor. Moreover, when PMCU decides to turn off the supply through power-rails to perform inaccessible power gating to a IP, the retention flops are forced to lose the stored content. The issue introduces a new method, i.e. save and restore of the functional registers through an alternate access interface before and after the power shut down across the IPs respectively. The novel validation methodology proposed here, will account for an end-to-end validation of PMCU-coordinated save and restore flow and will thereby also verify the retention strategy defined for a IP Subsystem.